In the manufacture of semiconductor devices, it is necessary to make electrical contact to certain regions or layers of the device. Typically, it is necessary to make contact to a region underlying a dielectric layer formed on the surface of a wafer during processing by first forming an opening or via in the dielectric over the region to be contacted. The opening may expose a device region within the silicon substrate, such as a source or drain, or may expose some other layer or structure, for example, an underlying metallization layer, local interconnect layer, or structure such as a gate. After the opening has been formed, thus exposing a portion of the region or layer to be contacted, the opening is filled with a conductive material deposited in the opening and in electrical contact with the underlying layer. In some cases, the fill material can be deposited and patterned coincidentally with the metallization for that layer. However, as geometries shrink, and the resulting openings in the dielectric layer have increasingly greater aspect ratios, filling the openings with the metallization layer becomes increasingly problematic.
To overcome the shortcomings involved in filling the openings with the metallization layer, a via fill process is employed, wherein a conductive plug of material is deposited in the vias prior to metallization. One approach is to use a blanket deposition and etchback. For example, a blanket tungsten layer is deposited, which fills all vias, and additionally coats the surface of the wafer. Typically, due to the high aspect ratios of the openings, the top surface is relatively planar, compared to the depressions in the underlying surface. The deposition is followed by a blanket etchback to remove the deposited tungsten from the surface of the substrate, leaving a tungsten filling or plug in the openings. The fill process is then followed by normal metallization to make contact to the fill material, thereby coupling the underlying region to the metallization. The tungsten is typically deposited by CVD using tungsten hexafluoride (WF.sub.6). One problem with this method is that a substantial amount of unused tungsten is formed and then etched from the surface of the wafer. Unfortunately, WF.sub.6 is a relatively expensive material, so that the cost of filling the vias is high relative to the small amount of tungsten actually remaining as part of the device. Another problem with the blanket deposition and etchback of tungsten is the microloading effect, wherein the etch rate drastically accelerates in the openings when the bulk of the film has been removed from the surface of the wafer, as is well known. A further problem with the blanket deposition and etchback of tungsten is poor adhesion due to the high internal stress of the blanket film. Finally, this method requires two processing steps (deposition and etch) and typically two different systems, to accomplish.
Another method for filling the vias is to employ a selective fill process. Depending upon the underlying material, various materials can be selectively deposited in the vias including, for example, doped polysilicon or metals such as tungsten, copper and nickel. When tungsten is used as the via fill, it is typically deposited on, for example, a titanium, titanium tungsten (TiW), or titanium nitride (TIN) seed layer which was deposited on the underlying region or metallization layer, for example, during previous processing steps. In order to grow a selective tungsten which completely fills the via, and which does not have unreasonably high contact resistivity, the seed layer quality must be carefully controlled. The seed layer cannot have any contamination such as polymer films or other organic material. Additionally, the TiW film should have no oxide formed thereon. However, it is difficult to maintain an oxide-free seed layer. For example, the methods used to remove polymer from the TiW seed layer tend to oxidize the TiW. A further problem encountered in selective fill process is that the dielectric layer through which the via is formed, often outgasses through the sidewall of the via, leading to contamination of the seed layer at the bottom of the via. An outgassing step after via formation, and prior to any seed layer clean may be performed to lessen the extent of outgassing. However, it is typically not possible to completely stop all outgassing from occurring during the via fill process.
Another problem with the selective fill method is that the selective fill grows from the bottom up, so that, in wafers having vias of varying depth, deep vias are not completely filled, while shallow vias become overfilled.
What is needed is a method of filling vias which utilizes the advantage of selective fill deposition, which provides for a contamination and oxide free seed layer, and which eliminates or reduces outgassing from the dielectric layer through the sidewall. Further, it is desirable that the method provide for uniform filling of the vias, regardless of their depth.